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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com st78c36/36a ecp/epp parallel printer port with 16-byte fifo april 2010 rev. 5.1.0 general description the st78c36/36a is a m onolithic parallel port interface for use with ibm pc compatible platforms. operation as a standard cent ronics printer port is the default, but software may re-configure the device to support bi-directional ibm ps/2 parallel port, enhanced parallel port (epp), or the extended capabilities port (ecp, as defined by hewlett packard and microsoft) modes. the ecp modes are supported by a 16 byte fifo that may be accessed by programmed i/o or dma cycles. applications ? printers, scanners and other peripherals ? zip drives and back up drives ? printer server ? embedded applications features ? ibm at bus compatible ? bi-directional port capability ? 16 byte fifo for ecp modes ? on-chip oscillator (st 78c36a, st78c36q64) ? software selectable interrupt (5, 7, or 9) and 8-bit dma channel (st78c36cq64) f igure 1. st78c36/36a b lock d iagram d0-d7 -ior -iow reset a0-a2 a10 -cs aen -ior, -iow -irqx iochrdy drqx pdir data bus & control logic register select logic interrupt control logic printer data ports pd0-pd7 printer control logic -strobe init -autofdx -selctin pe, select busy, -ack -error printer fifo registers inter connect bus lines & control signals clock & timing generator xtal1 xtal2 tc -dackx
f igure 2. st78c36/36a p in o ut a ssignments note: pinouts not to scale. the 64-lqfp package is physically smaller than the 44-plcc package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 n.c. -dack2 drq3 -dack3 d7 d6 d5 d4 d3 d2 d1 d0 aen -irq9 gnd vcc gnd drq2 tc pe -ack busy slct -error vcc -ior -iow a1 a0 drq1 n.c. n.c. n.c. -irq5 iochrdy -irq7 xtal1 xtal2 pdir -cs gnd reset -strobe -autofdx init -slctin n.c. n.c. st78c36cq64 64-lqfp gnd -dack1 a2 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 gnd a10 n.c. n.c. n.c. 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 drq3 -dack3 d7 d6 d5 d4 d3 d2 d1 d0 aen iochrdy -irq7 xtal1 xtal2 -cs gnd reset -strobe -autofdx init -slctin a2 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 gnd a10 tc pe -ack busy slct -error vcc -ior -iow a1 a0 st78c36acj44 44-plcc 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 drq3 -dack3 d7 d6 d5 d4 d3 d2 d1 d0 aen iochrdy -irq7 clock pdir -cs gnd reset -strobe -autofdx init -slctin a2 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 gnd a10 tc pe -ack busy slct -error vcc -ior -iow a1 a0 st78c36cj44 44-plcc ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus st78c36cj44 44-plcc 0 o c to 70 o c active st78c36acj44 44-plcc 0 o c to 70 o c active st78c36cq64 64-lqfp 0 o c to 70 o c eol st78c36/36a 2 ecp/epp parallel printer port with 16-byte fifo rev. 5.1.0
st78c36/36a 3 rev. 5.1.0 ecp/epp parallel printer port with 16-byte fifo pin description n ame 44- plcc pin # 64- lqfp pin # t ype d escription data bus interface a10 a2 a1 a0 29 39 41 40 36 46 53 52 i address select lines. a10 places the ecp control/status/data ports at 0x400 offset from the -cs decoded address. d7 d6 d5 d4 d3 d2 d1 d0 9 10 11 12 13 14 15 16 5 6 7 8 9 10 11 12 i/o data bus. bi-directional data port. -ior 43 55 i active low at bus i/o read strobe. -iow 42 54 i -cs 22 24 i chip select (active low). a low at this pin enables the parallel port / cpu data transfer operation. iochrdy 18 19 o i/o channel ready (internal pull-up / three stated active high). this pin goes low when the device requires addition clock cycles for read and write. -irq9 -irq7 -irq5 - 19 - 14 20 18 o interrupt request lines (three stated active low). aen 17 13 i dma address enable (active high). when this line is high, the dma controller has control of the address bus. drq3 drq2 drq1 7 - - 3 63 51 o active high at bus dma request for channels 3, 2 and 1 (internal pull- down three stated active high). a request is generated by bringing a drqx line to a high level. a drq x line is held high until the corre - sponding dma acknowledge ?dackx*? line goes low. -dack3 -dack2 -dack1 8 - - 4 2 47 i dma acknowledge signals for channels 3, 2 and 1 (internal pull-up /three stated active low). tc 6 62 i terminal count (active high). the st78c36 terminates the dma channel when a high pulse is detected.
st78c36/36a 4 ecp/epp parallel printer port with 16-byte fifo rev. 5.1.0 printer port interface pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 38 37 36 35 34 33 32 31 45 44 43 42 41 40 39 38 i/o bi-directional parallel port (three-state ) to transfer data in or out of the st78c36 parallel port. pd[7:0] are latched during output mode. output only for spp and ppf modes, bi-directional for all other modes. -strobe 25 27 o data strobe output (internal pull-up / th ree stated active low). this output indicates to the printer that valid data is available at the printer port (pd0- pd7). -autofdx 26 28 o automatic line feed (internal pull-up / three stated active low). when this signal is low the printer should automatically line feed after each line is printed. init 27 29 o initialize line printer (internal pull-up / three stated active low). when this signal is low, it causes the printer to be initialized. -slctin 28 30 o line printer select (internal pull-up / three stated active low). when this signal is low, it selects the printer. -error 1 57 i line printer error (internal pull-up / active low). this is an output from the printer to indicate an error by holding it low during error condition. slct 2 58 i line printer selected (internal pull-up / ac tive high). this is an output from the printer to indicate that the line printer has been selected. busy 3 59 i line printer busy (internal pull-up / acti ve high). an output from the printer to indicate printer is no t ready to accept data. -ack 4 60 i line printer acknowledge (internal pul l-up / active low). this input is pulsed low by the printer to indicate that data has been accepted success - fully. pe 5 61 i line printer paper empty (internal pull-up / active high). an output from the printer to indicate out of paper. pdir 21 23 o printer port direction indicator. high indicates device is in input mode, low indicates output mode. (s t78c36cj44 and st78c36cq64 only). system signals clock/ xtal1 20 21 i crystal oscillator input (st78c36acj44, st78c36cq64) or external clock input (st78c36cj44), nominal 24 mhz. xtal2 21 22 o crystal oscillator output, nominal 24 mhz. st78c36acj44 and st78c36cq64 only. reset 24 26 i system reset (active high). pin description n ame 44- plcc pin # 64- lqfp pin # t ype d escription
st78c36/36a 5 rev. 5.1.0 ecp/epp parallel printer port with 16-byte fifo 1.0 overview this device is designed around th e hewlett packard/microsoft specificat ion for extended capabilities port protocol with ?ecr mode 100? defined as e nhanced parallel port (epp) mode. the internal timing engines were designed around a 24 mhz reference, which can be supplied from an external source or by the built-in oscillator circuit (st78c36acj and st78c3 6cq64 only) with an appropriate crystal. at system reset, the device defaults to standard ibm pc compatible centronics printer mode (output only). the bi-directional ps/2, epp, and ecp modes can only be activated by programming the ecr mode field (this requires address bit a10 = 1, which is outside the normal isa i/o space). optional capabilities of the ecp sp ecification are set as follows: ecp defined interrupts are pulsed, low true (centronics -ack is non-pulsed, low true). pword size is forced to 1 byte. there is 1 byte in the transmitter that does not affect the fifo full bit (ecp modes). rle compression is not supported in hardware. irq channel is selectable as 5, 7, or 9 (st78c36cq64 only). dma channel is selectable as 1, 2, or 3 (st78c36cq64 only). fifo threshold is set at 8 (used only for non-dma access to the fifo). data 000 r/w 000, 001 data register ecp-afifo 000 w 011 ecp fifo (address) dsr 001 r all status register dcr 002 r/w all control register epp-aport 003 r/w 100 epp port (address) epp-dport 004 - 007 r/w 100 epp port (data) c-fifo 400 w 010 parallel port data fifo ecp-dfifo 400 r/w 011 ecp fifo (data) t-fifo 400 r/w 110 te s t f i f o cnfg-a 400 r 111 configuration register a cnfg-b 401 r/w 111 configuration register b ecr 402 r/w all extended control register vcc 44 16, 56 pwr power supply (+5v). gnd 23,30 15, 25, 37, 48, 64 pwr supply ground. port address r/w mode function pin description n ame 44- plcc pin # 64- lqfp pin # t ype d escription
st78c36/36a 6 ecp/epp parallel printer port with 16-byte fifo rev. 5.1.0 2.0 standard definitions x forward direction only. compatible mode: ?centronics? or standard mode. x reverse direction only. nibble mode: 4 bits at a time using status lines for data ?hewlett packard bi-tronics?. x bi-directional. epp: enhanced parallel port-used prim arily by non-prin ter peripherals. ecp: extended capability port-u sed primarily by new generatio n of printers and scanners. 3.0 internal registers 3.1 data register (data ) data bits 7-0: for host output cycles in spp mode (e cr mode 000) or ps/2 mode (ecr mode 001), da ta from the host is registered at the tra iling edge of -iow. on host input cycles, data at the periphe ral port is passed through to the host data bus. 3.2 ecp fifo address ( ecp-afifo ) ecp-afifo bits 7-0: this port is only available for programmed i/o (non-dm a), and only has significan ce for host write. data written to this port is stored in the fi fo if fifo-f = 0 and will be lost if fi fo-f = 1. a 9th fifo bit (tag) is set low on write. a read from this port is the same as a read at 400. 3.3 status register ( dsr ) this status register is read-only except for bit-0, and all bits are latched for the duration of -ior. dsr bit-0: if epp mode is not selected, this bit returns logic one. duri ng epp mode, bit-0 will return a high if the epp 10 msecond timeout elapsed during the last epp read or write cycle (this timeout also abort s the epp cycle). this status bit is cleared by exiting epp mode or by the host writing a high to bit-0 of this register. dsr bits 2-1: reserved, logic one. dsr bit-3: the true state of the -error pad. dsr bit-4: the true state of the slct pad. dsr bit-5: the true state of the pe(mpty) pad. dsr bit-6: the true state of the -ack pad. dsr bit-7: the complement of the busy pad.
st78c36/36a 7 rev. 5.1.0 ecp/epp parallel printer port with 16-byte fifo 3.4 control register ( dcr ) dcr bit-0: the complement of this bit drives -strobe, and the complement of the pad state is returned for read. dcr bit-1: the complement of this bit drives -autofd, and the complement of the pad state is returned for read. dcr bit-2: this bit drives init, and the pad state is returned for read. dcr bit-3: the complement of this bit drives -slctin, and th e complement of the pad state is returned for read. dcr bit-4: ack interrupt enable set to a high will generate an in terrupt when -ack is low. wh en either returns to a high state, this interrup t source will go in-active. this interrupt is not pulsed. dcr bit-5: peripheral port direction, out = 0 and in = 1. this bit is forced to logic zero by ecr modes 000 or 010. it can be written on ly in ecr mode 001, and will maintain that state if the ecr mode is changed to 011, 100, or 110. this bit must be set low for epp mode, which allows the host to control direction with -ior and -iow. the final port direction also drives pdir. dcr bits 6-7: reserved, logic zero. 3.5 epp address port ( epp-aport ) when epp mode is enabled, a ho st read or write with this port will result in a data tran sfer directly to/from the peripheral with -slctin active. direction is set by host read/write and will drive -s trobe low during a write if dcr bit 5 (dir) is not set high. 3.6 epp data port (epp-dport ) when epp mode is enabled, a ho st read or write with this port will result in a data tran sfer directly to/from the peripheral with -autofd active. direction is set by ho st read/write and will drive -strobe low during a write if dcr bit 5 (dir) is not set high. 3.7 parallel port data ( c-fifo ) this port is available for programmed i/o and dma access. data written to this port is stored in the fifo if fifo-f = 0 and will be lost if fifo-f = 1. data written to this port will be au tomatically transf erred to the peripheral with -strobe handshaking with busy. this port is only define d for write, host reads will interfere with fi fo read sequencing. 3.8 ecp data fifo ( ecp-dfifo ) this port is available for programmed i/o and dma access. data written to this port is stored in the fifo if fifo-f = 0 and will be lost if fifo-f = 1. a 9th fifo bi t (tag) is set high on write. data read from this port will undergo de -compression if the fifo tag bit and data bit-7 are both low. the byte containing the rle count is loaded into the rle counter and the succ eeding byte in the fifo will be returned to the host rle count + 1 times before the fifo read address is incremented. if a fifo under-run is incurred during host read, the last data byte is returned and fifo-e remains coherent.
st78c36/36a 8 ecp/epp parallel printer port with 16-byte fifo rev. 5.1.0 3.9 test fifo ( t-fifo ) this port is available for programmed i/o and dma access. data written to this port is stored in the fifo if fifo-f = 0 and will be lost if fifo-f = 1. during a read cycle from this port a fifo under- run will return last data read and fifo-e remains coherent. 3.10 configuration regi ster a ( cnfg-a ) this read-only register is available in ecr mode 111 only. cnfg-a bits 1-0: forced to logic zero, this field is don?t care for pword = 1 byte. cnfg-a bit-2: when transmitting, there is 1 byte waiting to be transmitted that does not affect fifo-f. cnfg-a bit-3: reserved, logic zero. cnfg-a bits 6-4: indicates pword = 1 byte (8-bit implementation). cnfg-a bit-7: indicates ecp interrupts are pulsed. 3.11 configuration regi ster b ( cnfg-b ) this register is available in ecr mode 111 only, and retu rns bits 0-5 as logic zero for the st78c36cj44. the st78c36cq64 will allow programmed selection of the interrupt and dm a channels after a system reset state of 001011 (bits 0-5). cnfg-b bits 2-0: with bit 2 forced low, select an 8-bit dma channel per the following table: t able 1: dma c hannel s election : c nfg - b b its [2:0] w rite to fifo r ead from fifo dma c hannel x00 000 3 x01 001 1 x10 010 2 x11 011 3 (default)
st78c36/36a 9 rev. 5.1.0 ecp/epp parallel printer port with 16-byte fifo cnfg-b bits 5-3: select an irq channel per the following table: t able 2: irq s election : c nfg - b b its [5:3] w rite to fifo r ead from fifo 000 001 7 001 001 7 (default) 010 010 9 011 001 7 100 001 7 101 001 7 110 001 7 111 111 5 cnfg-b bit-6: returns the true value of the selected irq pad. cnfg-b bit-7: indicates rle compression is not supported. 3.12 extended control register ( ecr ) the extended cont rol register has a system reset state of 10010101. t he significance of the bits is defined by the ecp specification as: ecr bit-0: this read-only bit returns fifo empt y status (fifo-e) and is forced high unless ppf, ecp, or tst mode is selected. 0 = at least one byte of data contains in the fifo. 1 = fifo is empty. ecr bit-1: this read-only bit returns fifo full status (fifo-f) and is forced low unless ppf, ecp, or tst mode is selected. 0 = at least one empty location is available in the fifo. 1 = fifo is full. irq
st78c36/36a 10 ecp/epp parallel printer port with 16-byte fifo rev. 5.1.0 ecr bit-2: when low, this bit (serviceintr) enables a pulsed interr upt and enables dma requests (if bit-3 is set). if the enabled interrupt occurs, this bit is automatically returned to a high. the interrupt conditions are: ecr bit-3 = dma dcr bit-5 = direction t able 3: dma condition 0 0 8 empty bytes in the fifo 0 1 8 filled bytes in the fifo 1 x dma terminal count (tc). ecr bit-3: this bit disables dma when set low. when se t high, a low on servicei ntr will enable dma requests. 0 = dma disabled, drqx pin is three-stated. 1 = dma enabled ecr bit-4: when low, this bit (-errintren) enables a pulsed interrup t if -error (-fault) is lo w. the interrupt is only enabled in ecp mode. ecr bits 7-5: this field can be set to any value if the current value is 000 or 001. if the current value is not 000 or 001, then the field can only be written to 000 or 001. the modes are defined as: t able 4: d escription of p arallel p ort m odes 000 spp standard centronics, output only. dcr bit-5 is forced to "0". 001 ps2 bi-directional ps/2 parallel port. fifo is disabled 010 ppf fifoed, output only. dcr bit-5 is forced to ?0?. 011 ecp ecp fifoed port with rle de-co mpression. fifo direction is controlled by dcr bit-5. 100 epp epp mode. 101 - reserved. 110 tst fifo test mode. fifo is accessible via tfifo register. 111 cfg configuration a/b register enable. dma dir condition mode name description
st78c36/36a 11 rev. 5.1.0 ecp/epp parallel printer port with 16-byte fifo 4.0 device operation 4.1 spp mode this is ecr mode 00 0 (system reset mode). in this output-only mode the host data is register ed to pd[7:0] at the tr ailing edge of -iow; pdir is driven low; -strobe, -autofd, init, and -slctin are open-drain; and all timing is managed by the host through dsr and dcr registers. 4.2 ps2 mode this is ecr mode 001. in this bi-directional mode the host output data is regist ered to pd[7:0] at the trailing edge of -iow, pdir is driven by dir to allow peripheral da ta input, -autofd, init, and -slctin are totem-pole, and all timing is managed by the host through dsr and dcr registers. 4.3 ppf mode this is ecr mode 010. in this output-only mode the host data is written to th e fifo with i/o writes to a ddress 400 or by dma writes; pdir is driven low; -autofd, init, and -slctin are totem-pole. fifo data is automatically registered to pd[7:0] whenever the fifo-e bit is low (data available), and timing is generated by controller logic that handshakes -strobe (controller) with busy (peripheral). 4.4 ecp mode this is ecr mode 011. in this bi-directional mode the host data is written to the fifo with i/o writes to address 000, 400 or dma; pdir is driven by dir (can only be set in ecr mode 001); -autofd, init, and -slctin are totem-pole. i/o writes to address 000 will write a low in to the fifo tag bit, while i/o writes to address 400 or dma will insert a high. 4.4.1 ecp forward mode (pdir = 0) fifo data is automatically registered to pd[7:0] whenever the fifo-e bit is low (data available), and timing is generated by controller logic that handshakes -strobe (controller) with busy (peripheral). data from the fifo tag bit is output on -autofd after be ing registered simultaneous with fifo data.
st78c36/36a 12 ecp/epp parallel printer port with 16-byte fifo rev. 5.1.0 4.4.2 ecp reverse mode (pdir = 1) pd[7:0] data and busy are latched into the fifo and tag bit respectively at the trailing edge of -autofd if fifo-f = 0. timing is generated by controller lo gic that handshakes -ack (peripheral) with -autofd (controller). 4.5 epp mode this is ecr mode 100. in this bi-directional mode, i/o writ es will latch host output data at the trailing edge of -iow, and peripheral input data will be latched at the trailing edge of -slctin or -autof d. pdir, and -strobe are driven by the state of -iow (dcr bits 5 and 0 must be set low); -autofd, init, and -slctin are totem-pole. epp mode allows buffered access between the pc bu s and the peripheral with ti ming provided by the peripheral via busy handshake into iochrdy. i/o cy cles with address 003 - 0 07 will immediately drive iochrdy low. -strobe will go low and pd[7:0] is allo wed to change (write cycles) after busy has been low for at least 60n second. (this delay may have elapsed pr ior to cycle initiation), i mmediately followed by a low driven on -slctin for address 003 or -autofd (dat astb*) for address 004 - 007 (read and write cycles). when busy returns high for a minimum of 60n second, iochrdy and the acti ve strobe will be driven high - allowing the host to comp lete the i/o transaction. to prevent a system stall, a 10 msecond timeout aborts t he cycle if it expires before busy returns high. this timeout also sets bit 0 of dcr, which is cleared by disabling epp mode or wr iting a high to dcr bit 0. 4.6 tst mode this is ecr mode 110. this mode allows data to be transferred (read or write in any direction) between th e fifo and host at address 400 or dma without activating the control interface (no data is transferred to/from the peripheral). pdir is driven by dir (can only be set in ecr mode 00 1); -autofd, init, and -slctin are totem-pole. performing i/o cycles in this mode allo ws software to test for the value of fifothreshold (ft) for both output and input directions. 4.7 cfg mode this is ecr mode 111. this mode enables i/o access to the configuration regi sters conf-a and conf-b and disables i/o access to the fifo. 4.7.1 irq the module has four sources of interrupt which may be directed to -irq5, -irq7, -irq9 (see conf-b) or externally jumpered. 1. when dcr bit 4 (aie) is high and -ack is low the interrupt is active. 2. when ecp mode is active, if ecr bit 4 is low when error transitions low or ecr bit 4 transitions low when -fault is low an inte rrupt pulse of at least 20 0n seconds will be generated. 3. in fifo modes (ppf, ecp, or tst) with ecr bit 3 (dma ) low, an interrupt pulse of at least 200n seconds will be generated when ecr bi t 2 (si) is set low if there are at le ast 8 empty bytes in the fifo and pdir = 0 or there are at least 8 filled by tes in the fifo and pdir = 1. this interrupt w ill automatically disable itself by setting ecr bit 2 high. 4. in fifo modes (ppf, ecp, or tst) with (dma requ est enabled), an interrupt pulse of at least 200n seconds will be generated when tc is received if pd-ack is low. this interrupt will automa tically disable itself and the dma request by setting ecr bit 2 high.
st78c36/36a 13 rev. 5.1.0 ecp/epp parallel printer port with 16-byte fifo 4.7.2 dma dma cycles occur only between the host and the fifo data port (address 400) for ppf, ecp, or tst modes. the selected drq(1, 2, or 3) will be driven high if ecr bit 3 (dma) is hi gh and ecr bit 2 (si) is low when {pdir = 0 and fifo-f = 0} or {pdir = 1 and fifo-e = 0} or tst mode is active. when the selected d-ack( 1, 2, or 3) is low, -iow will transfer host data to the fi fo and -ior will transfer fifo data to the host. the selected drq will be driven low to terminate the dma channel when {p dir = 0 and fifo-f = 1} or {pdir = 1 and fifo-e = 1} or ecr bit 2 (si) goes high (int errupt condition 4 above) or more than 32 consecutive dma data cycles (read or write) have occurred. fifo-f and fifo-e terminated cycles will automatically restart when their stat e returns low. consecutive cycle termination will automatically restart because the counte r is reset when the selected d-ack goes high. tc terminated cycles can only be restarted by the host setting ecr bit 2 (si) low again. 4.7.3 rle the module does not support rle compression (indicated by the ?0? in conf-b bit 7) but is required to support rle de-compression. the host may send compressed data to the peripheral by wr iting the rle length byte (bit 7 = 0) to address 000 (note: dma cannot be used for this byte) which will place a zero into the fifo tag bit. this must be followed immediately by the data byte being wr itten to the fifo at address 400. these bytes will be transferred to the peripheral in the normal manner. de-compression takes place if pdir = 1 when data is re ad from the fifo at address 000, 400 or dma. when a byte is read from the fifo, bits 0- 6 (length) are placed in a counter if data bit-7 and the fifo tag bit are both low. the subsequent byte in the fifo (data) is pres ented to the host count + 1 times before the fifo read pointer is advanced. t able 5: internal registers description 0 0 0 0 data port , ecp-afifo pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 0 0 0 1 dsr busy -ack pe slct error 1 1 1 0 0 1 0 dcr 0 0 dir int enable -slctin init -auto- fd -strobe 0 0 1 1 epp-aport ap-7 ap-6 ap-5 ap-4 ap-3 ap-2 ap-1 ap-0 1 0 0 0 epp-dport pda-7 pda-6 pda-5 pda-4 pda-3 pda-2 pda-1 pda-0 0 1 0 1 epp-dport pdb-7 pdb-6 pdb-5 pdb-4 pdb-3 pdb-2 pdb-1 pdb-0 0 1 1 0 epp-dport pdc-7 pdc-6 pdc-5 pdc-4 pdc-3 pdc-2 pdc-1 pdc-0 0 1 1 1 epp-dport pdd-7 pdd-6 pdd-5 pdd-4 pdd-3 pdd-2 pdd-1 pdd-0 1 x 0 0 conf-a ecp int type 0 0 1 0 fifo-f 0 0 1 x 0 1 conf-b rle irq input irq sel-2 irq sel-1 irq sel-0 dma sel-2 dma sel-1 dma sel-0 1 x 1 0 ecr mode sel-2 mode sel-1 mode sel-0 fault enable dma en/dis service int fifo full fifo empty a10a2a1a0registerd7d6d5d4d3d2d1 d0
st78c36/36a 14 ecp/epp parallel printer port with 16-byte fifo rev. 5.1.0 5.0 signal descriptions in various modes t able 6: ?centronics, spp? signal descriptions s ignal n ame s ignal t ype d escription -strobe o active low. indicates valid data is on the data lines. -autofd o active low. instructs the printe r to automatically insert a lin e feed for each carriage return. -slctin o active low. used to indicate to the printer that it is selected. init o active low. used to reset the printer -ack i a low asserted pulse used to indicate that the last character was received. busy i a high signal asserted by the printer to indicate that it is busy and cannot take data. pe i a high signal indicated that printer paper is empty. slct i a high signal indicates that printer is online. -error i asserted low to indicate that some error condition exists. pd0-pd7 o data.
t able 7: "nibble mode" signal descriptions s ignal n ame s ignal t ype n ibble m ode n ame d escription -strobe o -strobe not used for reverse data transfer. -autofd o hostbusy host nibble mode handshake signal. set low to indicate host is ready for nibble. set high to indicate nibble has been received. -slctin o 1284active set high when host is in a 1284 transfer mode. init o init not used for reverse data transfer. -ack i ptrclk set low to indicate valid nibble data, set high in response to "hostbusy" going high. busy i ptrbusy used for data bit-3, then bit-7. pe i ackdatareq used for data bit-2, then bit-6. slct i xflag used for data bit-1, then bit-5. -error i -dataavail used for data bit-0, then bit-4. pd0-pd7 o n/a not used. st78c36/36a 15 rev. 5.1.0 ecp/epp parallel printer port with 16-byte fifo 5.1 nibble mode data transfer cycle host signals ability to take data by asserting hostbusy low. peripheral responds by placi ng first nibble on status lines. peripheral signals valid nibble by asserting ptrclk low. host sets hostbusy high to indicate that it has received the nibble and is not ready for another nibble. peripheral sets ptrclk high to acknowledge host.
t able 8: ?epp mode? signal descriptions s ignal n ame s ignal t ype epp mode n ame d escription -strobe o -write active low. indicates a write operation, high for a read cycle -autofd o -datastb active low. indicates a data-read or data-write operation is in process. -slctin o -addrstb active low. indicates an address-re ad or address-write operation is in process. init o -reset active low. peripheral reset. -ack i -intr peripheral interrupt. used to generate an interrupt to the host. busy i -wait handshake signal. when low it indicates that is okay to start a cycle, when high it indicates that it is okay to end the cycle. pe i user defined slct i user defined -error i user defined pd0-pd7 o ad0-ad7 bi-directional address / data lines. st78c36/36a 16 ecp/epp parallel printer port with 16-byte fifo rev. 5.1.0 5.2 epp mode data transfer cycle program executes an i/o writ e cycle to epp data port-4. the -write line is asserted and the data is output to the parallel port. the -datastb is asserted, since -write is asserted low. the port waits for the acknowledge from the peripheral, -write deasserted. the -datastr is deasserted and epp cycle ends. -write is asserted low to indicate that the next cycle may begin.
t able 9: ?ecp mode? signal description s ignal n ame s ignal t ype ecp mode n ame d escription -strobe o hostclk used with periphack to transfer data or address information in the for - ward direction. -autofd o hostack provides command / data status in the forward direction. used with periphclk to transfer data in the reverse direction. -slctin o 1284active set high when host is in a 1284 transfer mode. init o -reversereq driven low to put the channel in reverse direction. -ack i periphclk used with hostack to transfer data in the reverse direction. busy i periphack used with hostclk to transfer data or address information in the forward direction. provides command / data status in the reverse direction. pe i -ackreverse driven low to acknowledge reverserequest. slct i xflag extensibility flag. -error i -periphreq set low by peripheral to indicate that reverse dat is available. pd0-pd7 i/o d0-d7 bi-directional data lines. st78c36/36a 17 rev. 5.1.0 ecp/epp parallel printer port with 16-byte fifo 5.3 ecp mode forward data and command transfer cycle host places data on the data lines and indicates a data cycle by setting hostack high. host asserts hostclk low to indicate valid data. peripheral acknowledge host by setting periphack high. host sets hostclk high. this is the edge that shou ld be used to clock the data in to the peripheral. peripheral sets periphack low to indicate that it is ready for the next byte. the cycle repeats, but this time it is command cycle because hostack is low. 5.4 ecp mode reverse data and command transfer cycle the host requests a reverse channel transfer by setting -reversereq low. the peripheral signals that it is okay to proceed by setting -ackreverse low. the peripheral places data on the data lines and indicates a data cycle by setting periphack high. peripheral asserts periphclk low to indicate valid data. host acknowledges by setting hostack high. peripheral sets periphclk high. this is the edge that should be used to clock the data in to the host. host sets hostack low to indicate that it is ready for the next byte. the cycle repeats, but this time it is a command cycle because periphack is low.
st78c36/36a 18 ecp/epp parallel printer port with 16-byte fifo rev. 5.1.0 ac electrical characteristics t a = 0 o c - 70 o c, vcc = 5.0v +/- 10%, un less otherwise specified. s ymbol p arameter l imits m in t yp m ax u nits t1 aen setup to command active 40 ns t2 command width 150 ns t3 aen hold from command inactive 60 ns t4 data access from -ior active 100 ns t5 data setup to -iow inactive 40 ns t6 data hold from command inactive 60 ns t7 pd7-0, -strobe, -autofd, init, -slctin delay from -iow inactive 100 ns t8 interrupt delay from -ack 60 ns t9 interrupt pre-charge pulse at release 10 ns t10 tc pulse width 60 ns t11 tc active to drqx inactive 100 ns t12 drqx active to -dackx active 0 ns t13 drqx inactive delay from -dackx active 100 ns t14 pd7-0 setup to -strobe active 600 ns t15 -strobe width 600 ns t16 pd7-0 hold from -strobe inactive 450 ns t17 pd7-0 hold from busy inactive 80 ns t18 -strobe active to busy active (handshake) 500 ns t19 busy inactive to -strobe active (cycle delay) 680 ns t20 pd7-0, -autofd setup to -strobe active 0 60 ns t21 pd7-0, -autofd hold from busy active 80 180 ns t22 -strobe inactive to busy inactive 0 ns t23 busy inactive to -strobe active 80 200 ns t24 -strobe active to busy active 0 ns t25 busy active to -strobe inactive 80 180 ns t26 pd7-0, busy setup to -ack active 0 ns t27 pd7-0 data hold from -autofd active 0 ns t28 -ack inactive to -autofd active 80 200 ns t29 -autofd active to -ack active 0 ns t30 -ack active to -autofd inactive 80 200 ns
st78c36/36a 19 rev. 5.1.0 ecp/epp parallel printer port with 16-byte fifo t31 -autofd inactive to -ack inactive 0 ns t32 host address setup to -iow active 40 ns t33 host address hold from -iow active 60 ns t34 host data setup to -iow active 0 20 ns t35 host data hold from -iow active 50 ns t36 -iow active to iochrdy low 0 20 ns t37 iochrdy high to host terminate (-iow inactive) 10 ns t38 -iow inactive to host command active (-iow or -ior) 40 ns t39 iochrdy pre-charge width at release 10 ns t40 host address setup to -ior active 40 ns t41 host address hold from -ior active 10 ns t42 host data setup to -ior inactive 0 20 ns t43 host data hold from -ior inactive 0 ns t44 -ior active to iochrdy low 0 20 ns t45 iochrdy high to host terminate (-ior inactive) 10 ns t46 -ior inactive to host command active (-iow or -ior) 40 ns ac electrical characteristics t a = 0 o c - 70 o c, vcc = 5.0v +/- 10%, un less otherwise specified. s ymbol p arameter l imits m in t yp m ax u nits
dc electrical characteristics t a = 0 o c - 70 o c, vcc = 5.0v +/- 10%, unless otherwise specified. s ymbol p arameter l imits m in t yp m ax u nit s c onditions v ilck clock input low level -0.5 0.6 v v ihck clock input high level 3.0 vcc v v il input low level -0.5 0.8 v v ih input high level 2.0 vcc v v ol output low level 0.4 v drq1-3, iochrdy: i ol = 14 ma d0-d7: i ol = 12 ma pdir: i ol = 4 ma all other outputs: i ol = 20ma v oh output high level 2.4 v d0-d7: i oh = -12ma pdir: i oh = -1ma all other outputs: i oh = -20ma icc avg. power supply current 7 9 ma i il input leakage 10 a i cl clock leakage 10 a i r internal pull up resistor current -85 -30 a for inputs -dack1-3, -error, slct, busy, -ack and pe st78c36/36a 20 ecp/epp parallel printer port with 16-byte fifo rev. 5.1.0 n ote : hewlett packard / microsoft compliance testing requires a ll ecp mode drivers to be push- pull and that they have an impedance controlled series resistor of at least 20 ohms and that the typical on resistance of the combination of the driver-resistor pair is in the 45-65 ohm range.
f igure 3. g eneral r ead /w rite t iming t1 t2 t3 a0-2, a10 aen -ior d0-7 7836-io t4 t5 t6 -iow t1 t2 t3 f igure 4. p arallel p ort t iming in spp, ps/2 m odes -iow pd0-7 -ack irqx 7836-spp t7 t8 t8 t9 st78c36/36a 21 rev. 5.1.0 ecp/epp parallel printer port with 16-byte fifo
f igure 5. h ost dma t iming in ecp m ode tc drqx aen dackx 7836-dma -iow,-ior t10 t11 t12 t13 t1 f igure 6. p arallel p ort fifo t iming t14 t15 t16 pd0-7 -strobe busy 7836-ppf t18 t17 t19 st78c36/36a 22 ecp/epp parallel printer port with 16-byte fifo rev. 5.1.0
f igure 7. p arallel p ort f orward t iming in ecp mode pd0-7 -strobe busy 7836-ecf -autofdx t20 t21 t22 t23 t24 t25 t22 f igure 8. p arallel p ort r everse t iming in ecp m ode pd0-7 -ack -autofdx 7836-ecr busy t26 t27 t28 t29 t30 t31 t28 st78c36/36a 23 rev. 5.1.0 ecp/epp parallel printer port with 16-byte fifo
f igure 9. a ddress or d ata w rite t iming in epp m ode a0-2, a10 7836-epw d0-7 iochrdy -iow t32 t33 t34 t35 t36 t37 t38 t39 f igure 10. a ddress or d ata r ead t iming in epp m ode a0-2, a10 7836-epr d0-7 iochrdy -ior t40 t41 t42 t43 t44 t45 t46 t39 st78c36/36a 24 ecp/epp parallel printer port with 16-byte fifo rev. 5.1.0
package dimensions (44 pin plcc) 44 lead plastic leaded chip carrier (plcc) rev. 1.00 1 d d 1 a a 1 d d 1 d 3 b a 2 b 1 e seating plane d 2 244 d 3 c r 45 x h 2 45 x h 1 note: the control dimension is the millimeter column inches millimeters symbol min max min max a 0.165 0.180 4.19 4.57 a 1 0.090 0.120 2.29 3.05 a 2 0.020 --- 0.51 --- b 0.013 0.021 0.33 0.53 b 1 0.026 0.032 0.66 0.81 c 0.008 0.013 0.19 0.32 d 0.685 0.695 17.40 17.65 d 1 0.650 0.656 16.51 16.66 d 2 0.590 0.630 14.99 16.00 d 3 0.500 typ. 12.70 typ. e 0.050 bsc 1.27 bsc h 1 0.042 0.056 1.07 1.42 h 2 0.042 0.048 1.07 1.22 r 0.025 0.045 0.64 1.14 st78c36/36a 25 rev. 5.1.0 ecp/epp parallel printer port with 16-byte fifo
package dimensions (64-lqfp) 48 33 32 17 116 49 64 d d 1 d d 1 b e a 2 a 1 a seating plane l c note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.055 0.063 1.40 1.60 a 1 0.002 0.006 0.05 0.15 a 2 0.053 0.057 1.35 1.45 b 0.005 0.009 0.13 0.23 c 0.004 0.008 0.09 0.20 d 0.465 0.480 11.80 12.20 d 1 0.390 0.398 9.90 10.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 a 0 7 0 7 st78c36/36a 26 ecp/epp parallel printer port with 16-byte fifo rev. 5.1.0
27 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent in fringement. charts and sc hedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assurances to its satisfaction that: (a) the ri sk of injury or damage has been minimized; (b) the us er assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2010 exar corporation datasheet april 2010. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. st78c36/36a rev. 5.1.0 ecp/epp parallel printer port with 16-byte fifo revision history d ate r evision d escription december 2003 rev 5.0.0 changed to standard style format. added revision history. added device status to ordering information. updated dc electrical characteristics. february 2004 rev 5.0.1 corrected the signal type of the -aut ofdx pin from i (input) to o (output). august 2005 rev 5.0.2 updated the 1.4mm-thick quad flat pack package description from "tqfp" to "lqfp" to be consistent with the jedec and industry norms. april 2010 rev 5.1.0 updated ac timing specs for t3, t6, t33, and t35. changed status of st78c36cq64 to "eol" per pdn 090507-01.

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